1. Field of the Invention
The present invention relates to a semiconductor device and a verify method for the semiconductor device, and more particularly relates to a semiconductor device having a memory module and determining whether a write operation to the memory module is normal by verify processing and to a verify method therefor.
2. Description of Related Art
A flash memory is has been widely used in recent years as a memory device (for example, a memory module) that is incorporated in a semiconductor device or attached externally thereto. Verify processing is performed to determine whether a write operation in a flash memory is normal. In the verify processing, write data to a memory module are taken as an expected value, read data that are obtained by reading again the written data are compared with the expected value, and whether the write operation is normal is determined by a match result of the write data and read data.
Japanese Unexamined Patent Application Publication No. H11-306774 discloses an example of a semiconductor memory device performing the verify processing. An example of processing flow (referred to hereinbelow as conventional verify processing flow) of verify processing of the semiconductor memory device disclosed in Japanese Unexamined Patent Application Publication No. H11-306774 is shown in FIG. 7. As shown in FIG. 7, in the conventional verify processing flow, a power source voltage supplied to a semiconductor memory device is detected (S101) prior to conducting the verify processing (steps S102 to S104). Then, verify processing (steps S102 to S104) is carried out, and when the verify result in step S104 indicates a no-good write (No branch of step S104), a retry write operation (steps S107 to S119) is performed. Where the verify result indicates a successful write (Yes branch of step S104), read setup processing is performed (S105) and the processing flow ends. Furthermore, when the verify result indicates a no-good write (No branch of step S104), where the number of cycles of retry write operation has reached a limit (Yes branch of step S105), the write operation is determined to be not good (step S120) and the processing is then ended via step S105.
Here, in the retry write operation in the conventional verify processing flow, a unit of write data to a memory cell is determined correspondingly to the power source voltage detected in step S101. In the conventional verify processing flow, the lower is the power source voltage, the smaller is the unit of write data that are written in one operation. In the example shown in FIG. 7, when the power source voltage is the lowest, write data to be written in one operation are taken as 4 bit and the write operation is performed in four cycles (steps S109 to S113). As the power source voltage increases, the bit number of write data is increased (steps S116 to S118 and step S119). In the conventional verify processing flow, the increase in write time at a low power source voltage is inhibited by controlling a unit of data during retry write operation correspondingly to the power source voltage.